Initial commit
This commit is contained in:
David 'Pixx' Zalesak
1
PCB/fp-info-cache
Normal file
1
PCB/fp-info-cache
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@@ -0,0 +1 @@
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||||
0
|
||||
3
PCB/fp-lib-table
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3
PCB/fp-lib-table
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@@ -0,0 +1,3 @@
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||||
(fp_lib_table
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||||
(lib (name moje_soucastky)(type KiCad)(uri ${KIPRJMOD}/libs/moje_soucastky.pretty)(options "")(descr ""))
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||||
)
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||||
20
PCB/libs/moje_soucastky.lib
Normal file
20
PCB/libs/moje_soucastky.lib
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@@ -0,0 +1,20 @@
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||||
EESchema-LIBRARY Version 2.4
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||||
#encoding utf-8
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||||
#
|
||||
# Mini_step_down_regulator
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||||
#
|
||||
DEF Mini_step_down_regulator U 0 40 Y Y 1 F N
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||||
F0 "U" 0 400 50 H V C CNN
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||||
F1 "Mini_step_down_regulator" 250 0 50 V V C CNN
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||||
F2 "" 0 0 50 H I C CNN
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||||
F3 "" 0 0 50 H I C CNN
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||||
DRAW
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||||
S -200 -350 200 350 0 1 0 N
|
||||
X GND 1 -100 450 100 D 50 50 1 1 w
|
||||
X VCC 2 100 450 100 D 50 50 1 1 w
|
||||
X GND 3 -100 -450 100 U 50 50 1 1 W
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||||
X 12V 4 100 -450 100 U 50 50 1 1 W
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||||
ENDDRAW
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||||
ENDDEF
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||||
#
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||||
#End Library
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||||
@@ -0,0 +1,20 @@
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||||
(module Mini_step_down_regulator (layer F.Cu) (tedit 5BDF54FE)
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||||
(fp_text reference REF** (at 0 -24.13) (layer F.SilkS)
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||||
(effects (font (size 1 1) (thickness 0.15)))
|
||||
)
|
||||
(fp_text value Mini_step_down_regulator (at 0 1.27) (layer F.Fab)
|
||||
(effects (font (size 1 1) (thickness 0.15)))
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||||
)
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||||
(fp_line (start -8.5 -22.5) (end 8.5 -22.5) (layer F.SilkS) (width 0.15))
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||||
(fp_line (start -8.5 -22.5) (end -8.5 0) (layer F.SilkS) (width 0.15))
|
||||
(fp_line (start 8.5 -22.5) (end 8.5 0) (layer F.SilkS) (width 0.15))
|
||||
(fp_line (start -8.5 0) (end 8.5 0) (layer F.SilkS) (width 0.15))
|
||||
(pad 1 thru_hole circle (at -6.604 -20.574) (size 1.524 1.524) (drill 0.762) (layers *.Cu *.Mask))
|
||||
(pad 1 thru_hole circle (at -4.064 -20.574) (size 1.524 1.524) (drill 0.762) (layers *.Cu *.Mask))
|
||||
(pad 2 thru_hole circle (at 6.636 -20.574) (size 1.524 1.524) (drill 0.762) (layers *.Cu *.Mask))
|
||||
(pad 3 thru_hole circle (at -4.064 -2.024) (size 1.524 1.524) (drill 0.762) (layers *.Cu *.Mask))
|
||||
(pad 4 thru_hole circle (at 6.636 -2.024) (size 1.524 1.524) (drill 0.762) (layers *.Cu *.Mask))
|
||||
(pad 2 thru_hole circle (at 4.096 -20.574) (size 1.524 1.524) (drill 0.762) (layers *.Cu *.Mask))
|
||||
(pad 3 thru_hole circle (at -6.604 -2.024) (size 1.524 1.524) (drill 0.762) (layers *.Cu *.Mask))
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||||
(pad 4 thru_hole circle (at 4.096 -2.024) (size 1.524 1.524) (drill 0.762) (layers *.Cu *.Mask))
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||||
)
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||||
3
PCB/sym-lib-table
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3
PCB/sym-lib-table
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@@ -0,0 +1,3 @@
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||||
(sym_lib_table
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(lib (name moje_soucastky)(type Legacy)(uri ${KIPRJMOD}/libs/moje_soucastky.lib)(options "")(descr ""))
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||||
)
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||||
253
PCB/tabule-cache.lib
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253
PCB/tabule-cache.lib
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@@ -0,0 +1,253 @@
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||||
EESchema-LIBRARY Version 2.4
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||||
#encoding utf-8
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||||
#
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||||
# 4xxx_4543
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||||
#
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||||
DEF 4xxx_4543 U 0 40 Y Y 1 L N
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F0 "U" -300 450 50 H V C CNN
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||||
F1 "4xxx_4543" -300 -450 50 H V C CNN
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||||
F2 "" 0 0 50 H I C CNN
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||||
F3 "" 0 0 50 H I C CNN
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||||
$FPLIST
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||||
DIP*W7.62mm*
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||||
SOIC*3.9x9.9mm*P1.27mm*
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||||
TSSOP*4.4x5mm*P0.65mm*
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||||
$ENDFPLIST
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||||
DRAW
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||||
S -300 400 300 -400 1 1 10 f
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||||
X ~LE 1 -500 -100 200 R 50 50 1 0 I
|
||||
X Qb 10 500 200 200 L 50 50 1 0 O
|
||||
X Qc 11 500 100 200 L 50 50 1 0 O
|
||||
X Qd 12 500 0 200 L 50 50 1 0 O
|
||||
X Qe 13 500 -100 200 L 50 50 1 0 O
|
||||
X Qg 14 500 -300 200 L 50 50 1 0 O
|
||||
X Qf 15 500 -200 200 L 50 50 1 0 O
|
||||
X VDD 16 0 600 200 D 50 50 1 0 W
|
||||
X D2 2 -500 100 200 R 50 50 1 0 I
|
||||
X D1 3 -500 200 200 R 50 50 1 0 I
|
||||
X D3 4 -500 0 200 R 50 50 1 0 I
|
||||
X D0 5 -500 300 200 R 50 50 1 0 I
|
||||
X PH 6 -500 -300 200 R 50 50 1 0 I
|
||||
X BL 7 -500 -200 200 R 50 50 1 0 I
|
||||
X VSS 8 0 -600 200 U 50 50 1 0 W
|
||||
X Qa 9 500 300 200 L 50 50 1 0 O
|
||||
ENDDRAW
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||||
ENDDEF
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||||
#
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||||
# Connector_Conn_01x02_Female
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||||
#
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||||
DEF Connector_Conn_01x02_Female J 0 40 Y N 1 F N
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||||
F0 "J" 0 100 50 H V C CNN
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||||
F1 "Connector_Conn_01x02_Female" 0 -200 50 H V C CNN
|
||||
F2 "" 0 0 50 H I C CNN
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||||
F3 "" 0 0 50 H I C CNN
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||||
$FPLIST
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||||
Connector*:*_1x??_*
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||||
$ENDFPLIST
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||||
DRAW
|
||||
A 0 -100 20 901 -901 1 1 6 N 0 -80 0 -120
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||||
A 0 0 20 901 -901 1 1 6 N 0 20 0 -20
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||||
P 2 1 1 6 -50 -100 -20 -100 N
|
||||
P 2 1 1 6 -50 0 -20 0 N
|
||||
X Pin_1 1 -200 0 150 R 50 50 1 1 P
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||||
X Pin_2 2 -200 -100 150 R 50 50 1 1 P
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||||
ENDDRAW
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||||
ENDDEF
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||||
#
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||||
# Connector_Conn_01x04_Female
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||||
#
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||||
DEF Connector_Conn_01x04_Female J 0 40 Y N 1 F N
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||||
F0 "J" 0 200 50 H V C CNN
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||||
F1 "Connector_Conn_01x04_Female" 0 -300 50 H V C CNN
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||||
F2 "" 0 0 50 H I C CNN
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||||
F3 "" 0 0 50 H I C CNN
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||||
$FPLIST
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||||
Connector*:*_1x??_*
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||||
$ENDFPLIST
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||||
DRAW
|
||||
A 0 -200 20 901 -901 1 1 6 N 0 -180 0 -220
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||||
A 0 -100 20 901 -901 1 1 6 N 0 -80 0 -120
|
||||
A 0 0 20 901 -901 1 1 6 N 0 20 0 -20
|
||||
A 0 100 20 901 -901 1 1 6 N 0 120 0 80
|
||||
P 2 1 1 6 -50 -200 -20 -200 N
|
||||
P 2 1 1 6 -50 -100 -20 -100 N
|
||||
P 2 1 1 6 -50 0 -20 0 N
|
||||
P 2 1 1 6 -50 100 -20 100 N
|
||||
X Pin_1 1 -200 100 150 R 50 50 1 1 P
|
||||
X Pin_2 2 -200 0 150 R 50 50 1 1 P
|
||||
X Pin_3 3 -200 -100 150 R 50 50 1 1 P
|
||||
X Pin_4 4 -200 -200 150 R 50 50 1 1 P
|
||||
ENDDRAW
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||||
ENDDEF
|
||||
#
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||||
# Connector_Conn_01x08_Male
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||||
#
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||||
DEF Connector_Conn_01x08_Male J 0 40 Y N 1 F N
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||||
F0 "J" 0 400 50 H V C CNN
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||||
F1 "Connector_Conn_01x08_Male" 0 -500 50 H V C CNN
|
||||
F2 "" 0 0 50 H I C CNN
|
||||
F3 "" 0 0 50 H I C CNN
|
||||
$FPLIST
|
||||
Connector*:*_1x??_*
|
||||
$ENDFPLIST
|
||||
DRAW
|
||||
S 34 -395 0 -405 1 1 6 F
|
||||
S 34 -295 0 -305 1 1 6 F
|
||||
S 34 -195 0 -205 1 1 6 F
|
||||
S 34 -95 0 -105 1 1 6 F
|
||||
S 34 5 0 -5 1 1 6 F
|
||||
S 34 105 0 95 1 1 6 F
|
||||
S 34 205 0 195 1 1 6 F
|
||||
S 34 305 0 295 1 1 6 F
|
||||
P 2 1 1 6 50 -400 34 -400 N
|
||||
P 2 1 1 6 50 -300 34 -300 N
|
||||
P 2 1 1 6 50 -200 34 -200 N
|
||||
P 2 1 1 6 50 -100 34 -100 N
|
||||
P 2 1 1 6 50 0 34 0 N
|
||||
P 2 1 1 6 50 100 34 100 N
|
||||
P 2 1 1 6 50 200 34 200 N
|
||||
P 2 1 1 6 50 300 34 300 N
|
||||
X Pin_1 1 200 300 150 L 50 50 1 1 P
|
||||
X Pin_2 2 200 200 150 L 50 50 1 1 P
|
||||
X Pin_3 3 200 100 150 L 50 50 1 1 P
|
||||
X Pin_4 4 200 0 150 L 50 50 1 1 P
|
||||
X Pin_5 5 200 -100 150 L 50 50 1 1 P
|
||||
X Pin_6 6 200 -200 150 L 50 50 1 1 P
|
||||
X Pin_7 7 200 -300 150 L 50 50 1 1 P
|
||||
X Pin_8 8 200 -400 150 L 50 50 1 1 P
|
||||
ENDDRAW
|
||||
ENDDEF
|
||||
#
|
||||
# Device_C
|
||||
#
|
||||
DEF Device_C C 0 10 N Y 1 F N
|
||||
F0 "C" 25 100 50 H V L CNN
|
||||
F1 "Device_C" 25 -100 50 H V L CNN
|
||||
F2 "" 38 -150 50 H I C CNN
|
||||
F3 "" 0 0 50 H I C CNN
|
||||
$FPLIST
|
||||
C_*
|
||||
$ENDFPLIST
|
||||
DRAW
|
||||
P 2 0 1 20 -80 -30 80 -30 N
|
||||
P 2 0 1 20 -80 30 80 30 N
|
||||
X ~ 1 0 150 110 D 50 50 1 1 P
|
||||
X ~ 2 0 -150 110 U 50 50 1 1 P
|
||||
ENDDRAW
|
||||
ENDDEF
|
||||
#
|
||||
# Device_R
|
||||
#
|
||||
DEF Device_R R 0 0 N Y 1 F N
|
||||
F0 "R" 80 0 50 V V C CNN
|
||||
F1 "Device_R" 0 0 50 V V C CNN
|
||||
F2 "" -70 0 50 V I C CNN
|
||||
F3 "" 0 0 50 H I C CNN
|
||||
$FPLIST
|
||||
R_*
|
||||
$ENDFPLIST
|
||||
DRAW
|
||||
S -40 -100 40 100 0 1 10 N
|
||||
X ~ 1 0 150 50 D 50 50 1 1 P
|
||||
X ~ 2 0 -150 50 U 50 50 1 1 P
|
||||
ENDDRAW
|
||||
ENDDEF
|
||||
#
|
||||
# MCU_Module_Arduino_Nano_v3.x
|
||||
#
|
||||
DEF MCU_Module_Arduino_Nano_v3.x A 0 40 Y Y 1 F N
|
||||
F0 "A" -200 1025 50 H V R CNN
|
||||
F1 "MCU_Module_Arduino_Nano_v3.x" -200 950 50 H V R CNN
|
||||
F2 "Module:Arduino_Nano" 150 -950 50 H I L CNN
|
||||
F3 "" 0 -1000 50 H I C CNN
|
||||
ALIAS Arduino_Nano_v2.x
|
||||
$FPLIST
|
||||
Arduino*Nano*
|
||||
$ENDFPLIST
|
||||
DRAW
|
||||
S -400 900 400 -900 0 1 10 f
|
||||
X D1/TX 1 -500 500 100 R 50 50 1 1 B
|
||||
X D7 10 -500 -100 100 R 50 50 1 1 B
|
||||
X D8 11 -500 -200 100 R 50 50 1 1 B
|
||||
X D9 12 -500 -300 100 R 50 50 1 1 B
|
||||
X D10 13 -500 -400 100 R 50 50 1 1 B
|
||||
X D11 14 -500 -500 100 R 50 50 1 1 B
|
||||
X D12 15 -500 -600 100 R 50 50 1 1 B
|
||||
X D13 16 -500 -700 100 R 50 50 1 1 B
|
||||
X 3V3 17 100 1000 100 D 50 50 1 1 w
|
||||
X AREF 18 500 200 100 L 50 50 1 1 I
|
||||
X A0 19 500 0 100 L 50 50 1 1 B
|
||||
X D0/RX 2 -500 600 100 R 50 50 1 1 B
|
||||
X A1 20 500 -100 100 L 50 50 1 1 B
|
||||
X A2 21 500 -200 100 L 50 50 1 1 B
|
||||
X A3 22 500 -300 100 L 50 50 1 1 B
|
||||
X A4 23 500 -400 100 L 50 50 1 1 B
|
||||
X A5 24 500 -500 100 L 50 50 1 1 B
|
||||
X A6 25 500 -600 100 L 50 50 1 1 B
|
||||
X A7 26 500 -700 100 L 50 50 1 1 B
|
||||
X +5V 27 200 1000 100 D 50 50 1 1 w
|
||||
X RESET 28 500 600 100 L 50 50 1 1 I
|
||||
X GND 29 100 -1000 100 U 50 50 1 1 W
|
||||
X RESET 3 500 500 100 L 50 50 1 1 I
|
||||
X VIN 30 -100 1000 100 D 50 50 1 1 W
|
||||
X GND 4 0 -1000 100 U 50 50 1 1 W
|
||||
X D2 5 -500 400 100 R 50 50 1 1 B
|
||||
X D3 6 -500 300 100 R 50 50 1 1 B
|
||||
X D4 7 -500 200 100 R 50 50 1 1 B
|
||||
X D5 8 -500 100 100 R 50 50 1 1 B
|
||||
X D6 9 -500 0 100 R 50 50 1 1 B
|
||||
ENDDRAW
|
||||
ENDDEF
|
||||
#
|
||||
# Transistor_FET_BS170
|
||||
#
|
||||
DEF Transistor_FET_BS170 Q 0 0 Y N 1 F N
|
||||
F0 "Q" 200 75 50 H V L CNN
|
||||
F1 "Transistor_FET_BS170" 200 0 50 H V L CNN
|
||||
F2 "Package_TO_SOT_THT:TO-92_Inline" 200 -75 50 H I L CIN
|
||||
F3 "" 0 0 50 H I L CNN
|
||||
ALIAS BS108 BS170
|
||||
$FPLIST
|
||||
TO?92*
|
||||
$ENDFPLIST
|
||||
DRAW
|
||||
C 65 0 111 0 1 10 N
|
||||
C 100 -70 11 0 1 0 F
|
||||
C 100 70 11 0 1 0 F
|
||||
P 2 0 1 0 30 -70 100 -70 N
|
||||
P 2 0 1 10 30 -50 30 -90 N
|
||||
P 2 0 1 0 30 0 100 0 N
|
||||
P 2 0 1 10 30 20 30 -20 N
|
||||
P 2 0 1 0 30 70 100 70 N
|
||||
P 2 0 1 10 30 90 30 50 N
|
||||
P 2 0 1 0 100 -70 100 -100 N
|
||||
P 2 0 1 0 100 -70 100 0 N
|
||||
P 2 0 1 0 100 100 100 70 N
|
||||
P 3 0 1 10 10 75 10 -75 10 -75 N
|
||||
P 4 0 1 0 40 0 80 15 80 -15 40 0 F
|
||||
P 4 0 1 0 100 -70 130 -70 130 70 100 70 N
|
||||
P 4 0 1 0 110 20 115 15 145 15 150 10 N
|
||||
P 4 0 1 0 130 15 115 -10 145 -10 130 15 N
|
||||
X D 1 100 200 100 D 50 50 1 1 P
|
||||
X G 2 -200 0 210 R 50 50 1 1 I
|
||||
X S 3 100 -200 100 U 50 50 1 1 P
|
||||
ENDDRAW
|
||||
ENDDEF
|
||||
#
|
||||
# moje_soucastky_Mini_step_down_regulator
|
||||
#
|
||||
DEF moje_soucastky_Mini_step_down_regulator U 0 40 Y Y 1 F N
|
||||
F0 "U" 0 400 50 H V C CNN
|
||||
F1 "moje_soucastky_Mini_step_down_regulator" 250 0 50 V V C CNN
|
||||
F2 "" 0 0 50 H I C CNN
|
||||
F3 "" 0 0 50 H I C CNN
|
||||
DRAW
|
||||
S -200 -350 200 350 0 1 0 N
|
||||
X GND 1 -100 450 100 D 50 50 1 1 w
|
||||
X VCC 2 100 450 100 D 50 50 1 1 w
|
||||
X GND 3 -100 -450 100 U 50 50 1 1 W
|
||||
X 12V 4 100 -450 100 U 50 50 1 1 W
|
||||
ENDDRAW
|
||||
ENDDEF
|
||||
#
|
||||
#End Library
|
||||
6511
PCB/tabule.kicad_pcb
Normal file
6511
PCB/tabule.kicad_pcb
Normal file
File diff suppressed because it is too large
Load Diff
1378
PCB/tabule.net
Normal file
1378
PCB/tabule.net
Normal file
File diff suppressed because it is too large
Load Diff
249
PCB/tabule.pro
Normal file
249
PCB/tabule.pro
Normal file
@@ -0,0 +1,249 @@
|
||||
update=Wed 22 May 2019 21:18:30 CEST
|
||||
version=1
|
||||
last_client=kicad
|
||||
[general]
|
||||
version=1
|
||||
RootSch=
|
||||
BoardNm=
|
||||
[cvpcb]
|
||||
version=1
|
||||
NetIExt=net
|
||||
[eeschema]
|
||||
version=1
|
||||
LibDir=
|
||||
[eeschema/libraries]
|
||||
[pcbnew]
|
||||
version=1
|
||||
PageLayoutDescrFile=
|
||||
LastNetListRead=tabule.net
|
||||
CopperLayerCount=2
|
||||
BoardThickness=1.6
|
||||
AllowMicroVias=0
|
||||
AllowBlindVias=0
|
||||
RequireCourtyardDefinitions=0
|
||||
ProhibitOverlappingCourtyards=1
|
||||
MinTrackWidth=0.2
|
||||
MinViaDiameter=0.4
|
||||
MinViaDrill=0.3
|
||||
MinMicroViaDiameter=0.2
|
||||
MinMicroViaDrill=0.09999999999999999
|
||||
MinHoleToHole=0.25
|
||||
TrackWidth1=0.5
|
||||
ViaDiameter1=1.2
|
||||
ViaDrill1=0.8
|
||||
dPairWidth1=0.2
|
||||
dPairGap1=0.25
|
||||
dPairViaGap1=0.25
|
||||
SilkLineWidth=0.15
|
||||
SilkTextSizeV=1
|
||||
SilkTextSizeH=1
|
||||
SilkTextSizeThickness=0.15
|
||||
SilkTextItalic=0
|
||||
SilkTextUpright=1
|
||||
CopperLineWidth=0.2
|
||||
CopperTextSizeV=1.5
|
||||
CopperTextSizeH=1.5
|
||||
CopperTextThickness=0.3
|
||||
CopperTextItalic=0
|
||||
CopperTextUpright=1
|
||||
EdgeCutLineWidth=0.15
|
||||
CourtyardLineWidth=0.05
|
||||
OthersLineWidth=0.15
|
||||
OthersTextSizeV=1
|
||||
OthersTextSizeH=1
|
||||
OthersTextSizeThickness=0.15
|
||||
OthersTextItalic=0
|
||||
OthersTextUpright=1
|
||||
SolderMaskClearance=0.051
|
||||
SolderMaskMinWidth=0.25
|
||||
SolderPasteClearance=0
|
||||
SolderPasteRatio=0
|
||||
[pcbnew/Layer.F.Cu]
|
||||
Name=F.Cu
|
||||
Type=0
|
||||
Enabled=1
|
||||
[pcbnew/Layer.In1.Cu]
|
||||
Name=In1.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In2.Cu]
|
||||
Name=In2.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In3.Cu]
|
||||
Name=In3.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In4.Cu]
|
||||
Name=In4.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In5.Cu]
|
||||
Name=In5.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In6.Cu]
|
||||
Name=In6.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In7.Cu]
|
||||
Name=In7.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In8.Cu]
|
||||
Name=In8.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In9.Cu]
|
||||
Name=In9.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In10.Cu]
|
||||
Name=In10.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In11.Cu]
|
||||
Name=In11.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In12.Cu]
|
||||
Name=In12.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In13.Cu]
|
||||
Name=In13.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In14.Cu]
|
||||
Name=In14.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In15.Cu]
|
||||
Name=In15.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In16.Cu]
|
||||
Name=In16.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In17.Cu]
|
||||
Name=In17.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In18.Cu]
|
||||
Name=In18.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In19.Cu]
|
||||
Name=In19.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In20.Cu]
|
||||
Name=In20.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In21.Cu]
|
||||
Name=In21.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In22.Cu]
|
||||
Name=In22.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In23.Cu]
|
||||
Name=In23.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In24.Cu]
|
||||
Name=In24.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In25.Cu]
|
||||
Name=In25.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In26.Cu]
|
||||
Name=In26.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In27.Cu]
|
||||
Name=In27.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In28.Cu]
|
||||
Name=In28.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In29.Cu]
|
||||
Name=In29.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In30.Cu]
|
||||
Name=In30.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.B.Cu]
|
||||
Name=B.Cu
|
||||
Type=0
|
||||
Enabled=1
|
||||
[pcbnew/Layer.B.Adhes]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.F.Adhes]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.B.Paste]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.F.Paste]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.B.SilkS]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.F.SilkS]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.B.Mask]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.F.Mask]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.Dwgs.User]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.Cmts.User]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.Eco1.User]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.Eco2.User]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.Edge.Cuts]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.Margin]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.B.CrtYd]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.F.CrtYd]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.B.Fab]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.F.Fab]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.Rescue]
|
||||
Enabled=0
|
||||
[pcbnew/Netclasses]
|
||||
[pcbnew/Netclasses/Default]
|
||||
Name=Default
|
||||
Clearance=0.2
|
||||
TrackWidth=0.5
|
||||
ViaDiameter=1.2
|
||||
ViaDrill=0.8
|
||||
uViaDiameter=0.3
|
||||
uViaDrill=0.1
|
||||
dPairWidth=0.2
|
||||
dPairGap=0.25
|
||||
dPairViaGap=0.25
|
||||
[pcbnew/Netclasses/1]
|
||||
Name=GND
|
||||
Clearance=0.4
|
||||
TrackWidth=0.75
|
||||
ViaDiameter=1.2
|
||||
ViaDrill=0.8
|
||||
uViaDiameter=0.3
|
||||
uViaDrill=0.1
|
||||
dPairWidth=0.2
|
||||
dPairGap=0.25
|
||||
dPairViaGap=0.25
|
||||
1898
PCB/tabule.sch
Normal file
1898
PCB/tabule.sch
Normal file
File diff suppressed because it is too large
Load Diff
Reference in New Issue
Block a user